Integrated circuits are continually being made smaller as demand for portability, computing power, memory capacity and energy efficiency in modern electronics grows. Therefore, the size of the integrated circuit constituent features, such as electrical devices and interconnect line widths, is also decreasing continually. The trend of decreasing feature size is evident in memory circuits and memory devices such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), ferroelectric (“FE”) memory, electrically erasable programmable read only memory (“EEPROM”), and so forth.
For example, flash memory is a type of EEPROM that typically comprises millions of individual circuit elements, known as memory cells, arranged into a densely-packed array. A flash memory cell typically comprises a transistor, a floating gate, and a control gate stacked above the floating gate. The floating gate, typically composed of polycrystalline silicon, is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer which is typically formed of an insulating oxide such as silicon oxide. Because charge is transferred across the dielectric layer by quantum mechanical tunneling, this dielectric layer is often referred to as a “tunnel oxide” layer. Such tunnel oxide layers are typically approximately 100 Å thick. Properties of the tunnel oxide are controlled to enable the ability to read and write by tunneling, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (“ONO”). Electrical access to the floating gate is therefore through capacitors. By decreasing the size of the transistor devices that form the individual memory cells, the size of a flash memory array can likewise be decreased. Thus, storage capacities can be increased by fitting more memory cells into a given circuit volume. Generally, flash memory arrays have a higher density of memory cells than DRAM arrays.
The distance between an identical point on two features in neighboring integrated circuit patterns, such as two features in a pattern of word lines or bit lines, is commonly referred to the “pitch” of the pattern. Integrated circuit features are typically defined by openings in, and are spaced apart from each other by, a material such as an insulator or a conductor. Thus, the concept of pitch can be understood as the sum of the width of a feature and the width of the space separating that feature from a neighboring feature.